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HBM2 has had a difficult 12 months. The memory standard hasn't followed the path of its predecessors. If information technology had, we should've already seen widespread rollouts from AMD and Nvidia across midrange and high-end products. Instead, AMD'southward Vega 56 and 64 are currently the only consumer GPUs to carry the retention standard at all.

1 of the rumors that dogged HBM2 last year was that clock speeds were well below what was targeted Indeed, neither of AMD'due south GPUs hit the expected 2Gbps per-pivot betoken rates (Hynix added two.0Gbps speeds to its HBM2 offerings in August 2016, so removed them in 2017). Samsung, nevertheless, may take establish a solution to this trouble, and plans to innovate new HBM2 clocked as high as ii.4Gbps per pin.

SAMSUNG HBM2_B

The new HBM2, codenamed Aquabolt, would exist clocked 1.2x higher than the previous HBM2 standard and 1.5x higher than the RAM on AMD's RX Vega 56. The other major advantage for college per-pin bandwidth is information technology theoretically reduces the need for additional HBM2 stacks.

This capability could be more of import than you lot might think. Rumors have suggested that the manufacturing difficulties with HBM2 take centered effectually the interposer — specifically, the difficulty of aligning and connecting the through-silicon vias that run through the retention stacks and into the interposer itself before connecting with the GPU. Some of you may retrieve the post-obit certificate from AMD's diverse discussions of HBM.

AMD-Interposer

That image just shows one HBM stack and its relation to an associated SoC dice. AMD's GPUs field ii HBM2 stacks, and up to four are possible. Samsung's two.4Gbps per-pivot signaling isn't going to be enough for a single-stack Vega 56 compared with the current model, just a unmarried 1024-bit HBM2 link @ 2.4Gbps would offer 307.2GB/s of retention bandwidth — ane.2x more than than the current bandwidth 256GB/s AMD'due south RX 580 delivers.

Samsung has as well managed to hit these increased clock speed without increasing HBM2'due south voltage. The company'southward first-generation HBM2 could run at 1.6Gbps at 1.2v or ii.0Gbps at 1.35v. These 2nd-generation chips can run at ii.4Gbps at 1.2v. Samsung's new chips used unspecified techniques related to TSV design and thermal control to connect the 5,000 TSVs per die and limit clock skew. It also added more than thermal bumps between the HBM2 dies to improve estrus dissipation and now adds a protective layer at the bottom of the HBM2 stack to improve physical strength.

Samsung did not give a ship date for its new Aquabolt fries, but did note Aquabolt is already in mass production. It'll take a while for new GPU designs to ship that utilize HBM2, merely it's possible the beleaguered standard has finally turned the corner.